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Serial Peripheral Interface (SPI)

Serial peripheral interface (SPI) is a short-distance serial communication interface that uses a high-speed clock (compared to I2C) and is suitable for higher data rates. SPI interface has different variants for serial communication, but the four-wire interface is the most popular one. These four signals are:

  • SCLK (serial clock)
  • MOSI (master-out-slave-in)
  • MISO (master-in-slave-out)
  • CS (chip select)

These signals might have other names as well, but the purpose remains the same. The SPI communication uses a master-slave architecture, where multiple slaves are connected to the master.

The SCLK is the serial clock that comes from the master for synchronization and data sampling. Therefore, the master should generate clock pulses whenever SPI communication happens.

The MOSI, or master-out-slave-in, is the serial data coming out of master and entering into the slaves.

The MISO, or master-in-slave-out, is the serial data entering into the master from the slaves.

The CS, or chip select, is an active low control signal from the master to a slave that enables that specific slave device. This signal is also known as slave select (SS). As there can be multiple slave devices connected to the same SPI bus, only one of the slave devices is active at one time.

Naming does not always matter, and you should confirm from the datasheet of the slave that the chip-enabling control signal is active-low or active-high and set it accordingly in the overlay.

The figure below shows three slave devices connected to a single SPI master. The SCLK, MOSI and MISO lines are shared between all slaves, while they each have their own CS signal. In this case, the master has three chip select signals to select one of the devices uniquely. At any given time, only one of the chip select signals should be asserted, and therefore, only one slave could read/write from the bus.

SPI configuration: 3 slave devices connected to single master

All Nordic chips support SPI in multiple modes (refer to the respective product specification of the SoC/SiP).

  • SPI: This is the SPI master interface.
  • SPIM: This is the SPI master interface with EasyDMA. The DMA interface (direct memory access) eliminates the need for CPU supervision while transferring a chunk of data and is more suited when large amounts of data are concerned or when we want the CPU to do something else.
  • SPIS: This is the SPI slave interface with EasyDMA. This is out of the scope of this lesson.

The figure below shows an SPI master-slave on an nRF SoC. PSEL here shows the configuration of the pin (pins are configured using respective configuration registers). Data coming from MISO is stored in the receive buffer, and the data from the transmit buffer goes onto the pin MOSI, while the clock signal is always generated by the master.

The SPI slave uses transmit (TXD) and receive (RXD) buffers and these are double-buffered to enable some degree of uninterrupted data flow in and out of the SPI. Furthermore, the SPI master does not implement support for chip select directly. Therefore, the CPU must use available GPIOs to select the correct slave and control this independently of the SPI master.

The SPI master supports SPI modes 0-3. These modes are based on the clock polarity (CPOL) and clock phase (CPHA). Polarity means whether the clock signal starts at logical low (CPOL=0) or logical high (CPOL=1) when the chip select is asserted. Phase in this context means that the data bit is sampled at which transition. If CPOL=0 then CPHA=0 means low-to-high transition, and CPHA=1 means high-to-low transition. In the other case, when CPOL=1, then CPHA=0 means high-to-low transition, and CPHA=1 means low-to-high transition. The figure below shows the sampling of the data bit for these different modes.

When using an SPI slave, we should consult the technical documents to see which SPI modes are supported by the end device (e.g sensor). We will take a closer look at this in the exercise section of this lesson.

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