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PMIC hardware integration

When designing ultra-low-power wireless devices using Nordic Semiconductor’s SoCs like the nRF54L Series, integrating a dedicated Power Management IC (PMIC) is essential for maximizing the battery life and system reliability. Whether you are using the nPM1300 for rechargeable Li-ion/Li-poly applications or the nPM2100 for primary battery designs (such as, coin cell or alkaline) , proper hardware integration defines the performance of your end product.

This section explores the key hardware integration considerations, focusing on rail separation, I/O voltage management, battery power budgets, and power sequencing.

Current requirements

Ensure that the selected rail can handle the peak current of the load. The nPM1300 provides two 200 mA Buck regulators and two 50 mA/100 mA LDO/Load switches. The nPM2100 provides up to 150 mA from its Boost regulator and 50 mA from its LDOSW. High-current peripherals (such as LEDs, motors) should be placed on a separate rail from the SoC to prevent heavy load transients from inducing voltage droop on the radio supply.

When planning the power budget for each rail or trying to determine which rails can be combined based on power consumption, looking at the average current is not enough. The designer must take the worst case scenario transient events into account to be sure not to overpower the regulator. Typically, a headroom of 30% should be enough, which means that the average current should be at most about 70% of the regulator’s maximum current rating. IC manufacturers have different solutions for evaluating the maximum current draw during transients. Nordic Semiconductor has the Online Power Profiler tool to help with this.

Fast current transients in the power rail may lead to the voltage dropping (or increasing) suddenly. For this reason, droop sensitive rails like the SoC VDD should not be combined with devices such as a motor driver, to avoid the VDD drooping possibly below the reset level. The linear resonant actuator (LRA) motor might create transient spikes of 100-200 mA in microseconds.

The following block diagram shows how an open-source Pebble 2 Duo smartwatch uses Nordic Semiconductor’s PMIC and SoC. The design files for this project can be found here.

I/O voltages and level shifting

A common hardware design challenge is matching the I/O logic levels between the SoC and external peripherals. Level shifters introduce additional cost and complexity, PCB area, and quiescent current leakage, and are usually undesirable in ultra-low-power designs.

Shared rail (Ideal): Operating the SoC and all peripherals at a unified voltage (for example, 1.8 V) allows them to share a single high-efficiency PMIC output (for example, BUCK1). This inherently solves the I/O mismatch and eliminates the need for level shifters.
Separate rails (Mixed-voltage): In some cases, the peripheral has separate VDD and VDDIO pins for the core and I/O, respectively. In such cases, it makes sense to use multiple PMIC rails to match the I/O voltage between devices to avoid using level shifters. For example, if the SoC runs at 1.8 V but a sensor requires 3 V to operate and has a separate VDDIO pin, one of the PMIC rails could be configured to supply 3 V and take the I/O supply from the SoC rail. In this case, close attention must be paid to sequencing, which will be covered later.

Design takeaway: Always attempt to unify I/O voltages. If mixed voltages are unavoidable, look for peripherals with dedicated VDDIO pins and power them from the same PMIC rail that supplies the nRF SoC.

Current requirements and battery power budgeting

Many devices are characterized by long periods of deep sleep punctuated by short, high-current pulses during RF transmission or sensor sampling. The battery’s Equivalent Series Resistance (ESR) plays a major role in the system stability.

Primary batteries (nPM2100)

Coin cells (for example, CR2032) have notoriously high ESR. Drawing a 15 mA Bluetooth LE TX pulse directly from a coin cell can cause the battery voltage to collapse, triggering a brownout reset (BOR).

The nPM2100 features a Prevent High Power (NOHP) mode, which prevents the boost from entering high power mode. This decreases the maximum current drawn from the battery. Combined with proper bulk capacitance (for example, 100 µF on both VBAT and VINT), the capacitor acts as a local energy reservoir, smoothing out the peak current drawn from the battery. This also increases battery life. Below are graphs and a table showing the improvements with different capacitor configurations.

The below values and graphs are from the nPM2100 hardware design guidelines.

Capacitors	Battery-life difference
Default capacitors: CVBAT: 10 µF + 1 nF COUT: 10 µF + 2.2 µF + 1 nF	Baseline
+100 µF at VINT	+2.7%
+100 µF at VBAT	+11.6%
+100 µF at VINT and VBAT	+17.9%

Response to Bluetooth LE event, default capacitors

Response to Bluetooth LE event, 100 µF added to the boost regulator input and output

ESR losses for each Bluetooth LE event in discharge test

Rechargeable batteries (nPM1300)

Li-ion and Li-poly batteries have much lower ESR and can easily handle peak currents. However, PCB trace inductance and PMIC input/output capacitance are still critical. A minimum of 10 µF on the buck inputs (PVDD) and outputs (VOUT1 and VOUT2) is required to ensure regulator stability and prevent voltage droops during sudden inrush currents when enabling load switches.

Power sequencing: GPIO vs. TWI control

Proper power sequencing ensures that peripherals are not back-fed through their I/O lines before their main power is applied, which can cause parasitic battery drain or latch-up states. Nordic PMICs offer two primary methods for controlling power rails dynamically.

TWI (I²C compatible) sequencing

Upon boot, the nRF SoC relies on the PMIC’s hardware default voltages (configured over the VSET pins). Once the SoC boots, it uses the Two-Wire Interface (TWI) to configure the PMIC registers.

Use case: Best for general initialization, configuring LDO output voltages, and entering deep sleep modes (Ship/Hibernate).
Drawback: TWI transactions take time. If a sensor needs to be powered on and off rapidly to save power, the I²C bus overhead might consume more energy than it saves.

GPIO sequencing

Nordic PMICs allow their regulators (bucks, LDOs, and load switches) to be mapped to dedicated PMIC GPIO pins. These pins can be driven directly by the nRF SoC’s GPIOs or by other logic pins on peripheral devices.

Use case: Best for latency-critical, highly precise sequencing. Using the nRF SoC’s Distributed Programmable Peripheral Interconnect (DPPI) and a hardware timer, the SoC can toggle a GPIO to enable the nPM1300 load switch before taking a sensor reading, and disable it immediately after.
Implementation: Configure the PMIC over the TWI at boot to assign LDSW1 to PMIC_GPIO0. From then on, toggling the SoC’s hardware pin instantly turns the sensor power on or off.

GPIOs, as well as TWI, can also be used to change the operation state of a regulator. This is useful, for example, when operating a buck in Hysteretic mode during idle operation, but switching to PWM mode for better and cleaner voltage regulation before an expected load event occurs.

Managing noise

Radio transceivers and high-resolution analog sensors are highly susceptible to power supply noise. Switching regulators (buck/boost) are highly efficient but can introduce voltage ripple.

For the SoC/radio: Nordic PMICs feature an automatic mode transition (Auto mode). During heavy loads or RF transmission, the PMIC automatically switches to a low-noise, fixed-frequency Pulse Width Modulation (PWM) mode, which is easier to filter due to the known switching frequency. During sleep, it reverts to a highly efficient Hysteretic mode.
For sensitive sensors: If your design includes highly sensitive analog sensors, consider powering them through the integrated LDO/load switch (LDOSW) rather than directly from a buck/boost output. The LDO provides a high Power Supply Rejection Ratio (PSRR) and filters out the switching noise.

While for some peripherals, an LDO might be the obvious choice due to the lower noise levels, some designs might still benefit from powering these with a buck due to better efficiency. If the sensor needs to be powered most of the time the device is on, it might be beneficial to sacrifice some accuracy to gain battery life. Also, if the peripheral is powered when the SoC is powered, it might make sense to use the same rail to save on regulators.

It is also possible to first regulate down from the battery with a buck converter and then further regulate this with an LDO. This way, energy is saved as the LDO does not waste as much energy as heat. For example, a buck regulator could regulate the battery voltage from about 3.7 V to 2.6 V. The LDO would further regulate this down to 1.8 V. However, this is often not feasible in area-constrained designs.

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