When designing ultra-low-power wireless devices with Nordic Semiconductor SoCs, like the nRF52, nRF53, or nRF54 Series, system power efficiency is the single most critical factor for maximizing battery life. While Nordic SoCs are highly optimized for power consumption, pairing them with a dedicated Power Management IC (PMIC) – such as the nPM1300 (buck/charger for rechargeable batteries) or the nPM2100 (boost for primary batteries) – unlocks the highest possible system efficiency.

This section explores the key hardware and software considerations for optimizing efficiency when integrating Nordic PMICs into your design. This section covers quiescent current, regulator operating modes, the impact of conversion ratios, SoC supply voltage selection, and battery life estimation using the Online Power Profiler (OPP).

Quiescent current (IQ) and system states

Quiescent current (IQ) is the current a PMIC consumes internally just to stay awake and regulate power, with no load attached. In low-power IoT devices and wearables, the system spends the majority of its time in sleep or standby states. Therefore, the PMIC’s IQ often dictates the absolute baseline of your battery life.

Nordic PMICs are designed with ultra-low IQ architectures and offer distinct system modes to minimize drain during different stages of the product lifecycle:

• Active mode: The PMIC is actively regulating voltage (for example, supplying the SoC). Even in active operation, Nordic PMICs maintain very low IQ (for example, the nPM2100 boost regulator consumes as little as 300 nA in ultra-low power mode).
• Hibernate mode: Designed for deep sleep. The PMIC disconnects unneeded loads but keeps a low-power wake-up timer running. For example, the nPM2100 consumes around 175–320 nA in hibernate mode, while the nPM1300 consumes around 500 nA.
• Ship mode: The lowest possible power state, used for shipping and storage to eliminate shelf-life battery drain. All outputs are disabled, and the PMIC waits only for a physical button press (or a break-to-wake event) to wake up. In this mode, the nPM2100 consumes just 35 nA, and the nPM1300 consumes around 370 nA.

The following table presents some typical values for IQ in different operation modes for nPM1300 and nPM2100.

Design Takeaway: Always implement Ship mode for the journey from the factory to the end user. Use the Hibernate mode for devices that only need to wake up infrequently (for example, once a day) to report sensor data.

Regulator operation modes: PWM vs. Hysteretic

Nordic PMIC bucks can operate in PWM, PFM, or Hysteretic mode. Understanding and using these modes correctly is essential for wireless designs.

• Hysteretic mode (Low power/PFM): In this mode, the regulator switches only when the output voltage drops below a certain threshold. It is highly efficient at light loads (for example, when the nRF54L SoC is in sleep mode or lightly advertising), because switching losses are minimized.
• PWM Mode (Pulse width modulation/High power): The regulator switches continuously at a fixed frequency (for example, 3.6 MHz on the nPM1300). While this consumes more baseline current, it provides exceptional load transient response and low voltage ripple. This is critical when the SoC’s radio is actively transmitting (TX) or receiving (RX), as predictable noise is easier to filter out, ensuring excellent RF coexistence.

By default, Nordic PMICs operate in Auto mode. The PMIC bucks autonomously transition between the Hysteretic mode (for sleep/light loads) and PWM mode (for heavy RF/processing loads). This ensures up to 95% efficiency across the entire load range without requiring the host SoC to micromanage the PMIC over the TWI. However, you can configure the PMIC to operate in the PWM mode through GPIO or TWI if a specific noise-sensitive sensor measurement is taking place.

Boost regulator modes (nPM2100)

The nPM2100 boost regulator is specifically designed to maximize the energy extracted from primary batteries (like CR2032 coin cells or alkaline AA/AAAs) across varying load conditions and battery lifecycles:

• Auto mode: The default setting. The PMIC automatically and seamlessly transitions between high-power, low-power, ultra-low-power, and pass-through modes based on the real-time load demand and the input battery voltage.
• High-power (HP) mode: Provides the maximum output current capability (up to 150 mA) required for heavy active loads. While it has the highest quiescent current, it ensures robust power delivery when the SoC needs it most.
• Low-power (LP) and ultra-low power (ULP) modes: These are highly efficient Hysteretic modes designed for light load conditions. They drastically reduce the quiescent current (down to 300 nA in the ULP mode).
• Pass-through (PT) mode: A highly efficient state engaged automatically when the battery voltage is at least 100 mV higher than the target output voltage (for example, when a fresh CR2032 battery is inserted). The PMIC bypasses the boost switching circuitry and passes the input directly to the output. This drops the quiescent current to a mere ~170 nA while still allowing up to 150 mA of load current.
• Prevent high power (NOHP): A crucial efficiency and safety feature for weak batteries with high equivalent series resistance (ESR), such as small coin cells. By forcing the PMIC to choose only between LP, ULP, or PT modes, you block it from entering the high-power mode. This prevents large peak current bursts that could cause a weak battery’s voltage to rapidly collapse and trigger an unwanted brownout reset.

Conversion ratio and component effects on efficiency

Efficiency is defined as output power divided by input power:

Eff = P_OUT/P_IN

In DC/DC regulators, the ratio between the input voltage (V_IN, the battery) and the output voltage (V_OUT, the system supply) affects how hard the regulator has to work.

• Buck regulators: Stepping down from a fully charged Li-ion battery (4.2 V) to 1.8 V will have a slightly different efficiency curve than stepping down to 3.0 V. Generally, efficiency is optimal when VIN​ and VOUT​ are closer together.
• Boost regulators (nPM2100): Stepping up a depleted alkaline battery (1.0 V) to 3.0 V requires higher peak inductor currents, increasing resistive losses compared to stepping a fresh 1.5 V battery up to 1.8 V.

Hardware impact: The external inductor choice heavily dictates the practical efficiency. As noted in the Nordic Hardware Design Guidelines (nPM2100, nPM130x), selecting an inductor with a low direct current resistance (DCR) – ideally < 400 mΩ – and adequate saturation current limits the energy lost as heat. Similarly, properly sizing the input/output capacitors reduces ESR losses and stabilizes the battery voltage during high-current Bluetooth LE TX pulses.

SoC supply voltage effect on overall efficiency

One of the easiest ways to radically improve system efficiency is to carefully select the PMIC’s output voltage (VOUT​). Nordic PMICs feature programmable output voltages (for example, 1.0 V to 3.3 V).

System trade-off:

• 1.8 V supply: Maximizes the SoC efficiency and battery life. Highly recommended if your external sensors and peripherals also support 1.8 V logic.
• 3.3 V supply: Required if you are interfacing with 3.3 V sensors, LEDs, or displays.

The power consumption difference between 1.8 V and 3.3 V VDD voltage can be estimated by using the online power profiler (OPP) tool and the PMIC data sheet. The following conditions are assumed:

• SoC: nRF54L15
• PMIC: nPM1300
• Application: Bluetooth Low Energy
• Radio TX power: 8 dBm
• Advertising Interval: 100 ms

For 1.8V VDD supply by using the OPP you can see the total average current to be 203 µA, so the input power is 365.4 µW. For 3.3 V VDD it would be 412.5 µW, which is about 13% higher.

The nPM1300 buck efficiency at 1.8 V for about 200 µA at VBAT=3.8 V is about 87%. For 3.3 V output at 125 µA and same VBAT the efficiency is about 94%. This means that for the nRF54L input powers mentioned above the PMIC input powers for these voltages are:

• 1.8 V: 365.4 µW/0.87 = 420 µW
• 3.3 V: 412.5 µW/0.94 = 439 µW

This shows that for this application using 3.3 V input for the nRF54 supplied by nPM1300 buck uses 4.5% more power per Bluetooth LE cycle.

If your design requires a mix of voltages, you can use the dual-buck outputs of the nPM1300: set BUCK1 to 1.8V to efficiently power the nRF SoC, and set BUCK2 to 3.0 V to power external peripherals, disabling BUCK2 via GPIO or TWI when the peripherals are not in use.

Some Nordic SoCs, such as the nRF54L Series have the maximum input voltage of 3.6 V at the VDD pin. Therefore, an external regulator is necessary when powered by batteries exceeding this voltage, such as Li-Ion and Li-Po. In this case, it is always better to use high efficiency regulator like the nPM1300 bucks to regulate as low as possible. For the nRF54L VDD pin, the minimum voltage level is 1.7 V and 1.75 V is required at power-on reset.Typically it is the best to supply 1.8V to this pin for maximum efficiency and proper operation also at power-on reset.

This efficiency difference between the SoC integrated regulator and PMIC regulator is partially due to the process node. The SoCs are manufactured on cutting-edge 22 nm process node, which is great for logic and memory but are not as suitable for power management circuits. By contrast, the nPM1300 is manufactured on a much larger 180 nm process node. This larger node is specifically optimized for power electronics. It creates robust transistors that handle higher voltages (like 4.2 V from a Li-ion battery) with virtually no leakage and highly efficient switching characteristics.

Estimating battery life with the Online Power Profiler (OPP)

Theoretical efficiency is good, but empirical estimation is better. As covered earlier in Lesson 1, Nordic provides the Online Power Profiler (OPP) to help you visualize how PMIC efficiency and SoC supply voltage translate to real-world battery life.

How to use the OPP for system efficiency:

1. Select your SoC and protocol: Choose your target device (nRF54L15) and your wireless protocol (for example, Bluetooth LE).
2. Configure the voltage: Change the supply voltage slider between 1.7 V and 3.6 V. This is the voltage at the VDD pin.
3. Check the total average current: You can now see the total average current in the current consumption box. At first glance you can see that the total average current increases when input voltage is decreased, which could seem like the device is also depleting the battery faster. To see the correct effect on battery life you must calculate the total average power.
4. Incorporate PMIC efficiency: You can calculate the total average power based on the total average current shown in the current consumption box and the input voltage selected. Now, the PMIC can be included in the calculation by taking the appropriate efficiency figure from the data sheet that matches these conditions.

As a simplified example: For nRF54L15 select Voltage 1.8 V. The total average current is 67 µA. Now, you can calculate the power consumed from the battery when a PMIC is used as follows:

P_in = (1.8 V * 67 µA)/Eff_PMIC, where Eff_PMIC is the PMIC efficiency at 1.8 V and 67 µA load current.

For the nPM1300, the efficiency would be about 94% at 3.8 V battery level. This leads to input power of 128 µW.

Summary

To extract the maximum battery life out of a Nordic SoC-based design using Nordic PMICs:

1. Leverage PMIC sleep states: Always use the Ship mode for storage and the Hibernate mode for ultra-long sleep intervals.
2. Trust auto mode: Allow the PMIC to automatically toggle between the Hysteretic and PWM modes to get the best of both worlds (ultra-low IQ during sleep, low noise during RF events).
3. Drop the voltage: Set the PMIC output to 1.8 V rather than 3.0 V if your peripherals allow it, massively reducing the SoC’s active power draw.
4. Follow hardware guidelines: Use low-DCR inductors and proper capacitor placement to minimize resistive losses during high-current RF pulses.
5. Profile your power: Use the Nordic Online Power Profiler to estimate the battery life.