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Exercise 3 – Measuring the impact of RAM retention settings

In this exercise, you will learn how memory retention affects current consumption in the nRF54L Series SoCs. These SoCs support flexible RAM retention configurations in different power modes.

Since a Bluetooth LE device typically sleeps for no more than 1-2 seconds, our main focus will be on System ON, including IDLE mode. You will also learn how to manually disable retention for selected RAM blocks and emulate the nRF54L10 and nRF54L05 SoCs (with less available RAM) on an nRF54L15 device (with the most available RAM).

The nRF Connect SDK can be used to optimize current consumption even further by disabling unused RAM blocks.

Important

This exercise supports only the nRF54L15 DK and the nRF54LS05 DK, as they support SoC variant emulation.

Exercise steps

In the GitHub repository for this course, go to the base code for this exercise, found in l5/l5_e3.

This base code is a Bluetooth LE advertising sample, with a 1-second advertising interval.

Full RAM retention

Let’s first observe the average current consumption and idle current consumption with full RAM retention, which is the case for the base code for this exercise.

1. Build and flash the base code to your DK and observe the power consumption.

Observe and note the average current consumption in your application. In our case, it’s around 8.74 μA. Let’s also take a look at the average idle current consumption, around 2.33 μA idle current.

2. Inspecting RAM retention settings.

The following blocks are assigned to an nRF54L15 SoC:

The RAM retention configuration is stored in the MEMCONF register. All the settings for the sections you will work with are stored in blocks 0-7 (all in POWER[0]). As the changes are related to System ON only, we are interested in the CONTROL register.

See all the sections in the table:

2.1 Debugging RAM retention registers.

Build the base code application again. When you pause the execution, you can see that all RAM blocks are retained (you can see the “ON” state on corresponding block in the MEMCONF.POWER.CONTROL register).

3. Configure the SoC variants.

It is easy to emulate the smaller nRF54L10/nRF54L05 SoC on an nRF54L15 DK, using a different devicetree and other configuration files. Overlay files contain the definition of memory regions, including RAM and RRAM. The overlay file (nrf54l15.dtsi) is available in the {SDK}/zephyr/dts/vendor/nordic/ folder. Note the differences in the variants.

3.1 Compile the exercise for the nRF54L15 variant.

Check the devicetree overlays for the selected variant, build the application, and compare the memory report results.

nRF54L15.dtsi:

...
&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(188)>;
	ranges = <0x0 0x20000000 DT_SIZE_K(188)>;
};
...

Copy

...
&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(188)>;
	ranges = <0x0 0x20000000 DT_SIZE_K(188)>;
};
...

Devicetree

Select the build target:

See the compilation results:

Memory region         Used Size  Region Size  %age Used
           FLASH:      204608 B      1420 KB     14.07%
             RAM:       31240 B       188 KB     16.23%
        IDT_LIST:          0 GB        32 KB      0.00%

Terminal

3.2 Compile the exercise for the nRF54L05 variant.

Select the nRF54L05 variant (which has less RAM available, as you can see in the overlay file below):

nRF54L05.dtsi

&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(96)>;
	ranges = <0x0 0x20000000 DT_SIZE_K(96)>;
};

Copy

&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(96)>;
	ranges = <0x0 0x20000000 DT_SIZE_K(96)>;
};

Devicetree

Select the build target:

See the compilation results:

Memory region         Used Size  Region Size  %age Used
           FLASH:      204672 B       492 KB     40.62%
             RAM:       31240 B        96 KB     31.78%
        IDT_LIST:          0 GB        32 KB      0.00%

Copy

Memory region         Used Size  Region Size  %age Used
           FLASH:      204672 B       492 KB     40.62%
             RAM:       31240 B        96 KB     31.78%
        IDT_LIST:          0 GB        32 KB      0.00%

Terminal command

SoC variant	Build target	dtsi file location	SRAM size
nRF54LM20DK
– nRF54LM20B	nrf54lm20dk/nrf54lm20b/cpuapp	nRF54LM20A/B	512 KB
– nRF54LM20A	nrf54lm20dk/nrf54lm20a/cpuapp	nRF54LM20A/B	512 KB
nRF54L15DK
– nRF54L15	nrf54l15dk/nrf54l15/cpuapp	nRF54L15	256 KB
– nRF54L10	nrf54l15dk/nrf54l10/cpuapp	nRF54L10	192 KB
– nRF54L05	nrf54l15dk/nrf54l05/cpuapp	nRF54L05	96 KB
nRF54LS05DK
– nRF54LS05B	nrf54ls05dk/nrf54ls05b/cpuapp	nRF54LS05B	96 KB
– nRF54LS05A	nrf54ls05dk/nrf54ls05a/cpuapp	nRF54LS05A	64 KB
nRF54LV10DK
– nRF54LV10A	nrf54lv10dk/nrf54lv10a/cpuapp	nRF54LV10A	192 KB

Using the nRF54L15 DK and the proper build target allows you to check if the application can be optimized for the variant you want to use in your end product.

For other nRF54L Series SoCs, the table below can be used to identify the variants and the SRAM memory configuration.

3.3 Build the application for the nRF54L05 variant.

Although the proper overlay files are used by the linker to properly handle the memory area dedicated to the selected variant, this does not influence the initial value of the MEMCONF registers.

You can verify this using an nRF Connect debug session and the peripheral viewer.

3.4 Set a breakpoint on the printk("Starting Bluetooth Peripheral LBS sample\n");.

More on this: See Debugging in nRF Connect for VS Code in the nRF Connect SDK Intermediate course for more information on how to do this.

3.5 Start a debug session in nRF Connect for VS Code by clicking Debug in the ACTIONS view.

Note

Ignore the warning “Debug option not enabled” and click Debug anyway. The Kconfig selections in the prj.conf file are CONFIG_DEBUG_OPTIMIZATIONS=y and CONFIG_DEBUG_THREAD_INFO=y.

3.6 Make sure to set the Breakpoint at the line printk(“Starting Bluetooth Peripheral LBS sample\n”).

3.7 Click Continue.

Execution should stop at the breakpoint:

3.8 Examine the MEMCONF register.

3.9. Reset the board (e.g: using Reset button ) and observe the current consumption.

Notice no major changes in idle current consumption.

4. RAM retention settings configuration

After selecting the SoC variants, you can configure the RAM retention settings in the application. For this task, use the nrf_memconf_ramblock_control_mask_enable_set() function from the nrfx library. The library allows for easy configuration of the retention of the individual RAM sections.

For the nRF54L05 only, sections 0, 1, and 2 from the RAM block 0 should be enabled, so you can create a bitmask disabling the other sections.

4.1 Include the nrf_memconf library and create a memory bitmask to disable unused sections.

Add the following lines in main.c

#include <hal/nrf_memconf.h>
#define RAM_96KB_DIS_SECTION_BITMASK 0x000000F8

Copy

#include <hal/nrf_memconf.h>
#define RAM_96KB_DIS_SECTION_BITMASK 0x000000F8

C++

4.2 Disable unused memory blocks.

Disable unused memory blocks by adding the following line in the main() function

nrf_memconf_ramblock_control_mask_enable_set(NRF_MEMCONF,0,RAM_96KB_DIS_SECTION_BITMASK,false);

Copy

nrf_memconf_ramblock_control_mask_enable_set(NRF_MEMCONF,0,RAM_96KB_DIS_SECTION_BITMASK,false);

C++

4.3 After building (nrfl54l15dk/nrf54l05/cpuapp board target) and flashing the application, you can observe the results.

4.4 Check the RAM retention settings in a debug session (like in step 3.4):

Disabling unused RAM blocks reduced the idle current consumption significantly.

5. Disabling unused RAM using nRF Connect SDK.

To optimize current consumption even further you can use the RAM power-down library from the nRF Connect SDK. The library uses the application’s RAM allocation to automatically disable unused RAM sections.

As your application requires ~31 KB of RAM you need only one section (when using static memory allocation only). Use the library and examine the results.

5.1 Enable the RAM power-down library in the prj.conf file using the following Kconfig option

CONFIG_RAM_POWER_DOWN_LIBRARY=y

Copy

CONFIG_RAM_POWER_DOWN_LIBRARY=y

Kconfig

5.2 Power down unused RAM. Power down unused RAM within the nRF54L05 RAM sections range (in addition to previously disabled sections) in the main() file:

power_down_unused_ram();

Copy

power_down_unused_ram();

C++

5.4 Examine the idle current consumption and the MEMCONF configuration.

5.5 Check the RAM retention settings in a debug session (like in step 3.4)

Using the library, you disabled two unused RAM blocks. When combined with the previously disabled sections outside of the nRF54L15 RAM range, it reduces the current consumption even further.

Alternatively, you can skip the MEMCONF configuration (step 4.1) and use only the RAM power-down library to disable all unused RAM sections by building the app for the nrf54l15dk/nrf54l15/cpuapp board target. This way, the library has access to the retention settings for the whole range according to the selected target definition.

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Designing Low-Power Bluetooth LE Products

Exercise 3 – Measuring the impact of RAM retention settings

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