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Lesson 2 – Power domains, event system, and GPIO

Overview

In this lesson, we will explore the structure of the power domains in the nRF54L Series. This structure allows for independent power on and off of large sections of a SoC to optimize energy consumption.

Then, we will cover intra- and cross-domain communication (event system) through the Distributed Programmable Peripheral Interconnect (DPPI) and DPPI Bridges (PPIB). This system enables different peripherals to interact with each other autonomously without requiring CPU involvement.

Additionally, the lesson will cover how different peripherals efficiently access system memory (RAM) through EasyDMA. This feature offloads data transfers from the CPU to save power and improve performance. Finally, we will explore the configuration and control of GPIO ports and pins across multiple domains. We will also cover the key rules of pin mapping for the nRF54L Series devices.

Objective

  • Gain a working understanding of the power domains structure in the nRF54L Series.
  • Learn about intra- and cross-domain communication (event system), DPPI, and PPIB.
  • Examine how peripherals access memory through easyDMA without CPU intervention.
  • Understand the GPIO ports’ capabilities and essential pin planning rules on the nRF54L Series.

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