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EasyDMA

While the event system allows for peripherals to interact with each other autonomously without the CPU, Easy Direct Access Memory (EasyDMA) is implemented by a number of peripherals on the nRF54L Series to provide direct access to RAM. EasyDMA is intended to enable peripherals to interact directly with system memory (RAM) as a bus manager, without requiring intervention from the CPU. This function facilitates efficient data transfers, reduces real-time processing demands on the CPU, and enhances both system performance and power efficiency. It is important to note that EasyDMA cannot access non-volatile memory.

This concept is illustrated in the following example figure, where READER is reading data from RAMc, while WRITER is writing data to RAMa and RAMb (each RAM being separate bus subordinates).

RAM on the nRF54L Series

The RAM on the nRF54L Series is divided into regions (RAM00, RAM01), with each region further divided into sections. This structure reduces latency when both the Arm CPU and FLPR are running and also supports flexible power management, enhancing power efficiency, as demonstrated in Lesson 5, where we explore memory retention across various sleep modes. Each section has a separate power and retention control for the System ON and System OFF modes. This functionality allows for managing RAM content during sleep modes and powering down unused sections to save energy.

Note

If the FLPR is used, RAM01 should be reserved for FLPR code and data, as well as non-time-critical application data. RAM00 should be used for time-critical data, such as EasyDMA buffers and application data accessed by low-latency ISRs.

nRF54LM20A | nRF54LM20B
RAM organization on the nRF54LM20A | nRF54LM20B
nRF54L15 | nRF54L10 | nRF54L05
RAM organization on the nRF54L15 | nRF54L10 | nRF54L05
nRF54LV10A
RAM organization on the nRF54LV10A
nRF54LS05A | nRF54LS05
RAM organization on the nRF54LS05A | nRF54LS05B

EasyDMA Channels and Buffers

There are several peripherals on the nRF54L Series that handle large amount of data use EasyDMA for efficient data handling. These include Serial Communication Interfaces, the Radio, Cryptographic accelerators, Analog (SAADC), and PWM.

Some peripherals are designed with multiple EasyDMA instances to provide dedicated channels, such as separate channels for reading and writing data. Data transfers are configured using pointer (.PTR) and maximum count (.MAXCNT) registers. The .PTR register specifies the start address of the RAM buffer, and .MAXCNT defines the maximum number of bytes to transfer.

Some peripherals are equipped with the following functionalities:

  • Double-Buffering: For some peripherals, the .PTR and .MAXCNT registers are double-buffered in hardware. This allows software to update these registers for the next transfer immediately after the current one has started (for example, after a STARTED event), preparing for a continuous stream of operations without interruption.
  • Array List Mode: Some peripherals support EasyDMA in an Array List mode for channels with a LIST register. In this mode, data is handled as a linear array in RAM, with items stored sequentially. For example, the SPIM peripheral uses this feature for both TX and RX in its EasyDMA. This mode allows the hardware to automatically move to the next buffer in the list, eliminating the need to manually configure the .PTR (by software, involving the CPU) for each memory chunk, which is very useful for efficient and continuous data streaming.

Once an EasyDMA transfer is complete, the CPU can read the AMOUNT register to determine the number of bytes successfully transferred. Events like END, STOPPED, READY, or specific DMA-related events (for example, DMA.RX.END, DMA.TX.END) indicate that EasyDMA has finished accessing the RAM.

To learn more about EasyDMA, see the EasyDMA documentation. You can also read the datasheet for each peripheral you are interested in. As different peripherals implement different EasyDMA features based on their needs.

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