nRF54L Series Express

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Power and clock management

The nRF54L Series comes with a flexible set of regulators and power management components to ensure the best performance in time-sensitive applications and the lowest possible power use when prioritizing battery life.

The power and clock management system continuously monitors the power and clock resources requested by various components within the system. To achieve the lowest power consumption possible, the system evaluates the requests, starts and stops clock sources, and chooses the most optimal regulator operation modes.

Let’s start by looking at the overview of the clock and the voltage regulators.

Power and clock management

Voltage regulators

The nRF54L Series requires an external power source, VDD (1.7V to 3.6V), which provides voltage levels to GPIOs and acts as a source for the main regulator. This regulator is crucial as it adjusts the internal voltage levels required for all the power domains, RRAM, and radio module. During the startup procedure, the regulator operates in LDO mode, which should not be used beyond initial startup due to efficiency concerns. It then switches to DC/DC to ensure the best power efficiency. The external components are necessary for stable operation in DC/DC mode. Detailed specifications and diagrams for these components can be found in the Reference circuitry documentation.

Note

Although most of the nRF54L Series SoCs support 1.7V to 3.6V VDD, the Series includes a low-voltage SoC (nRF54LV10A) that operates on 1.2V to 1.7V (VDDL). The nRF54LV10A SoC is equipped with a boost regulator. It is responsible for stepping up the voltage and providing the proper voltage level for the internal SoC components that need a higher voltage level than VDDL. The voltage on the GPIOs will be equal to VDDL.

PMIC

A power management IC (PMIC) can be used to provide a proper voltage level or more advanced power regulation, especially in battery-operated devices. The PMICs not only control the charging process, but also monitor the battery’s state of charge to prevent unexpected power loss. The nRF54L Series can be combined with one of Nordic Semiconductor’s power management ICs. PMICs also provide a set of unique features that are further described on the Power Management IC Products – nordicsemi.com page.

The PMICs can be categorized based on two battery types:

  • Primary batteries – In this case, the power management IC enables fuel gauging to provide accurate battery state of charge (0 to 100%). It uses the algorithms developed by Nordic Semiconductor, designed for various non-rechargeable batteries on the market such as 1.5 V nominal AA or AAA alkaline batteries (in 1S or 2S configurations), as well as coin-cell and button-cell batteries, like the CR2032 and LR44. You can find a detailed practical guide on the nPM2100 Fuel Gauge page.
  • Rechargeable batteries (Li-ion, Li-Poly, LiFePO) – For this type of battery, the PMIC estimates the state of charge (0 to 100%) by considering the battery model, temperature, voltage, and current consumption. The battery model can be created using the nPM1300 or nPM1304 Evaluation Kit, which allows for detailed analysis tailored to the specific battery in use. You can find more details on the Generating a battery model page. In addition, all the PMICs working with this battery type are equipped with a built-in battery charger.

The Power Management ICs overview compares all the PMICs offered by Nordic`s Semiconductor and helps to select the most suitable component for the required application.

Clock sources and oscillators

The nRF54L Series uses 2x main clocks that generate the necessary clock sources for all peripherals and system components.

  • 32.768 kHz Low frequency clock (LFCLK)
  • 128MHz High frequency clock (HFCLK)

The low-frequency clock is a source for the Global real-time clock (GRTC) and the SYSCOUNTER. It can be powered by a low-frequency crystal oscillator (LFXO), which requires an external 32.768 kHz crystal. As the source provides the best accuracy and is the only clock source running in the System OFF mode, it is the recommended SoC configuration.

In scenarios where the design footprint is a critical factor and an external crystal can not be used, a low-frequency clock can be driven by:

  • 32.768 kHz low frequency RC oscillator (LFRC)
  • 32.768 kHz low frequency source synthesized from HFCLK (LFSYNT)

Additionally, when using an internal RC oscillator as a source for the low-frequency clock, the accuracy might be impacted by temperature variations. To address this, the SoCs include a calibration procedure that uses a high-frequency clock as a reference.

The high-frequency clock is a clock source for the MCU power domain and the CPU clock, which can be divided to operate at 64MHz frequency. It also acts as the base to provide 32MHz, 16MHz, and 1MHz clocks in the system through the HFCLK controller. All high-frequency clocks are available in System ON mode, and two possible sources of that clock play a vital role in the system. Before the necessary 32 MHz crystal oscillator becomes operational, the system uses a 128 MHz internal oscillator, which has a short startup time.

Clock control

Depending on the application, the high-frequency crystal oscillator frequency tolerance requirements vary from 40 ppm to 60 ppm. It is crucial to equip the crystal oscillators with properly selected capacitors. Similar to the internal oscillator setup, the system allows for reducing footprint size and the number of external components by providing configurable internal capacitors for both low and high-frequency oscillators. The external ones can also be used.

Power modes

Having covered regulators and clock sources, it is time to look into the nRF54L power modes: System ON, System OFF, and System Hibernation. The system provides flexible options to switch between low current consumption and optimal performance, making it adaptable for a wide range of applications based on the specific requirements.

System OFF

Let`s start with the mode providing the lowest current consumption. In System OFF mode, all high-frequency clocks are disabled, and all ongoing tasks and DMA transactions are stopped. Depending on the configuration, RAM sections can be retained. The only active component is the low-frequency oscillator (LFXO), which provides the clock to GRTC. The GRTC is capable of waking up the device from this mode. Additionally, several more peripherals can also wake the device:

  • GPIO – Wakes the device by generating a DETECT signal.
  • Low power comparator – Activates the device upon detecting an ANADETECT signal.
  • NFCT – Wakes the device when a field is detected.

System OFF is additionally emulated during a debugging session to ensure that all resources required for debugging are available. Initiating a debug session or resetting the device using the reset pin automatically wakes up the device and puts it into System ON mode. When the device changes from System OFF to System ON mode, a system reset occurs. See more details on the RESET — Reset control page.

System ON

In System ON mode, the power for all system modules is managed by the power and clock management unit. It dynamically switches the power to the RUN state for domains currently in use and disables it when all operations are completed, transitioning to IDLE state. The behavior of the chip is determined by the selected power strategy, also known as the sub-power mode. The nRF54L Series can be configured to either prioritize performance or save energy. Within System ON, you can select one of the following sub-power modes:

  • Constant latency – This mode ensures that both the CPU wakeup latency and the PPI task response are constant and kept at a minimum.
  • Low-power (default) – The automatic power management system optimizes power usage by selecting the most efficient supply option. While this mode achieves the lowest possible power consumption, it does so at the expense of variable CPU wakeup latency and PPI task response time.

The System ON is also the default mode following a power-on reset. Before the device goes into System ON mode, it undergoes a reset procedure.

System hibernation mode for shipping and storage

In System Hibernation mode (available only in nRF54LV10A), all device functions are shut off to keep minimal power consumption (less than 50 nA). This reduces battery leakage during transport and storage. The device in this mode can be awakened by pin reset procedure. In addition, Hibernation mode has the following effects on a device:

  • RAM is not retained
  • Debugger is disconnected
  • GPIO pins retain their configured states and must be released and reconfigured when the device wakes up

System reset

System reset in the nRF54L Series can be triggered by various events and requests beyond just powering the device (power-on reset) or using the reset pin. These triggers include:

  • Brownout – Occurs when the VDD supply voltage drops below the brownout reset threshold.
  • CTRL-AP – Configurable to initiate one of three types of resets:
    • Soft reset
    • Pin reset
    • Hard reset (during erase operation)
  • Watchdog and CPU Lockup
  • Wakeup from System OFF – Triggered by the peripheral designated as a wake-up source, such as GRTC.
  • Tamper detection – Activates a reset when an internal or external physical attack is detected.
  • Voltage glitch detection – Similar to brownout, this reset occurs when VDD or internal digital voltage drops below safe thresholds.

The reset behavior varies depending on the trigger, and different peripherals and modules may be affected differently. The following table outlines which modules are impacted by each reset source event:

 Reset overview

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