The general-purpose input and output pins are grouped into ports with up to 32 pins each.

All GPIO ports support the following basic functionality:

• Pin direction: Configures each pin as input to read external signals or as output to generate signals.
• Pull-up and pull-down: Configures internal resistors to keep a pin at a stable logic high or low when not actively driven.
• Drive strength: Sets how much current a pin can source or sink, which affects the rise time (how quickly the voltage goes from low to high) and the fall time (how quickly the voltage goes from high to low).

A GPIO port can support additional features, including:

• Analog pins: Determines whether a pin can be used to read an analog signal.
• Wake-up source: Can be configured to wake up the device from the System OFF state.
• Tasks & Events (through GPIOTE): Allows for changes in the output state by triggering supported tasks (set, clear, toggle) and enables detection of pin state changes through corresponding events (rising edge, falling edge, or any change).
• Pin sense mechanism: Pins can be individually configured to generate a logical level detection signal, which can be consumed by the CPU as interrupts or by other peripherals.

In this topic, we will cover the available GPIO ports on the different SoCs in the nRF54L Series, their capabilities, and essential pin planning rules. We will also shed light on GPIOTE support and how it relates to the event system.

nRF54L Series Packages/GPIOs options

As we covered in Lesson 1, the nRF54L Series is offered in various QFN and CSP packages that come with different GPIO counts. The table below summarizes the GPIO count for each SoC package.

nRF54L15 | nRF54L10 | nRF54L05 available ports and features

Three of the power domains, MCU, PERI, and LP, have their own GPIO ports (P2, P1, and P0, respectively), while the RADIO domain lacks a GPIO port. P1 and P0 share several features, but P2 stands out with distinct characteristics. Let’s take a look at the features of each of these ports.

• GPIO port 2 (P2) – MCU domain
  • The number of pins on this port depends on the package used. For the QFN48 package, there are 11 pins: P2.00 to P2.10
  • Pins on this port are the fastest on the chip and are intended for high-speed signals such as trace or fast serial communication.
  • The maximum speed for signals on P2 is 64 MHz.
  • The available options include standard, high drive, and extra high drive.
  • P2 pins cannot wake the system from sleep, and it does not include the GPIO SENSE or DETECT mechanism or GPIOTE functionality. This means that interrupt support is not available on P2 pins when they are configured as general-purpose GPIO.
  • Peripherals located in the MCU domain, such as SPIM00 and UARTE00, use dedicated pins on P2.
  • Dedicated pins for TRACE and FLPR (for emulated peripherals like sQSPI) are also located on P2.
  • Selected pins on P2 can also be used by certain serial interfaces (SPIM, SPIS, UARTE) located in the peripheral domain. However, this configuration is considered less power-efficient as it increases power consumption by requiring the Constant Latency mode to be enabled, which keeps the clock running constantly.
• GPIO port 1 (P1) – PERI domain
  • The number of pins on this port depends on the package used. For the QFN48 package, there are 15 pins: P1.00-P1.14.
  • The maximum speed for signals on P1 is 8 MHz.
  • The available options include standard and high drive.
  • P1 pins can wake the system up from System ON or System OFF sleep.
  • Includes analog input pins (AIN0-AIN7), which are shared by the ADC (SAADC) and the COMP/LPCOMP in the LP domain.
  • PWM peripherals are only available on P1 pins.
  • P1 supports the pin sense mechanism and is associated with GPIOTE20.
  • Dedicated pins for TAMPC when tamper detection is used.
  • Dedicated RADIO pins are on P1 when using Bluetooth direction finding.
  • Has dedicated NFC antenna pins on P1 configured as NFC antenna pins from reset. These can be changed as general-purpose GPIO as shown in this sample.
  • Has dedicated pins for the LFXO (Low-frequency 32.768 kHz crystal oscillator) when using an optional 32.768 kHz external crystal.
• GPIO port 0 (P0) – LP domain.
  • The number of pins on this port depends on the package used. For the QFN48 package, there are 5 pins: P0.00-P0.04
  • The maximum speed for signals on P0 is 8 MHz.
  • The available options include standard and high drive.
  • P0 pins can wake the system up from System ON or System OFF sleep.
  • P0 supports the pin sense mechanism and is associated with GPIOTE30.
  • Has dedicated pins for GRTC when using its CLKOUT32K and PWM output.

The following diagram shows the peripherals associated with each power domain and their corresponding GPIO ports for the QFN48 package, illustrating how the nRF54L QFN48 integrates power domains and GPIO ports:

nRF54LM20A | nRF54LM20B available ports and features

In addition to P2, P1, and P0 ports, the nRF54LM20A and nRF54LM20B SoCs introduce an additional GPIO port, Port 3 (P3), expanding the capabilities and flexibility of the device compared to the nRF54L15|10|05 models. The nRF54LM20A and nRF54LM20B also include fixed-function pins for USB.

The SoC CSP98 package of the nRF54LM20A|B includes a total of 66 GPIOs.

• GPIO port 3 (P3) – PERI domain (nRF54LM20A|B – CSP Only)
  • Only available on the nRF54LM20A|B – CSP98 package. For the CSP98, there are 13 pins: P3.00 to P3.12
  • The maximum speed for signals on P3 is 8 MHz.
  • The available options include standard and high drive.
  • P3 pins can wake the system up from System ON or System OFF sleep.
  • P3 supports the pin sense mechanism and is associated with GPIOTE20.

nRF54LV10A available ports and features

The nRF54LV10A is a low-voltage wireless SoC optimized for wearable biosensors, medical devices, and other applications powered directly by silver-oxide coin cells. It does not include GPIO Port 2 (P2). It only features P1 and P0, and the pins on these ports support low voltages from 1.2 to 1.7 V.

• GPIO port 2 (P2) – MCU domain
  • Not available on the nRF54LV10A.
• GPIO port 1 (P1) – PERI domain
  • The number of pins on this port depends on the package used. For the QFN48 package, there are 26 pins: P1.00-P1.25.
  • The maximum speed for signals on P1 is 8 MHz.
  • The available options include standard and high drive.
  • P1 pins can wake the system up from System ON or System OFF sleep.
  • Includes analog input pins (AIN0-AIN7), which are shared by the ADC (SAADC) and the COMP/LPCOMP in the LP domain.
  • P1 supports the pin sense mechanism and is associated with GPIOTE20.
  • Dedicated pin for GRTC CLKOUTFAST when used.
  • Dedicated RADIO pins are on P1 when using Bluetooth direction finding.
  • Has dedicated pins for the LFXO (Low-frequency 32.768 kHz crystal oscillator) when using an optional 32.768 kHz external crystal.
• GPIO port 0 (P0) – LP domain.
  • Only available in the QFN48 package, and there are 5 pins: P0.00-P0.04
  • The maximum speed for signals on P0 is 8 MHz.
  • The available options include standard and high drive.
  • P0 pins can wake the system up from System ON or System OFF sleep.
  • P0 supports the pin sense mechanism and is associated with GPIOTE30.
  • Has dedicated pins for GRTC when using its CLKOUT32K and PWM output.

nRF54LS05A | nRF54LS05B available ports and features

The nRF54LS05A and nRF54LS05B are entry-level SoCs in the nRF54L Series that provide the series’ core capabilities: robust Bluetooth LE connectivity, ultra-low power consumption, and easy-to-use software; while being optimized for the development of simple, cost-efficient Bluetooth LE end products

• GPIO port 2 (P2) – MCU domain
  • Not available on the nRF54LS05A and nRF54LS05B.
• GPIO port 1 (P1) – PERI domain
  • The number of pins on this port depends on the package used. For the QFN48 package, there are 32 pins: P1.00-P1.31.
  • The maximum speed for signals on P1 is 8 MHz.
  • The available options include standard and high drive.
  • P1 pins can wake the system up from System ON or System OFF sleep.
  • Includes analog input pins (AIN0-AIN3), which can be used by the ADC (SAADC)
  • P1 supports the pin sense mechanism and is associated with GPIOTE20.
  • Dedicated pin for GRTC CLKOUTFAST when used.
  • Has dedicated pins for the LFXO (Low-frequency 32.768 kHz crystal oscillator) when using an optional 32.768 kHz external crystal.
• GPIO port 0 (P0) – LP domain.
  • Only available in the QFN48 package, and there are 5 pins: P0.00-P0.04
  • The maximum speed for signals on P0 is 8 MHz.
  • The available options include standard and high drive.
  • P0 pins can wake the system up from System ON or System OFF sleep.
  • P0 supports the pin sense mechanism and is associated with GPIOTE30.
  • Has dedicated pins for GRTC when using its GRTC CLKOUT32K and PWM output.

Summary of port capabilities

Essential pin planning rules

When planning pin assignments for your project, it is crucial to adhere to specific guidelines to ensure optimal performance and power efficiency. Here’s a breakdown of the essential pin planning rules for managing GPIO ports and their associated peripherals:

1. Matching peripherals to their domains – Peripherals must use pins in their own power domain. However, there are some exceptions:
   • COMP/LPCOMP in the LP domain must use the analog pins in P1.
   • Selected pins on P2 can also be used by certain serial interfaces (SPIM, SPIS, UARTE) located in PERI, although this configuration is less power-efficient as discussed before.
   • GRTC in the PERI has dedicated pins on P0 when using its clock and PWM output.
2. Dedicated clock pins – Some peripherals with clock signals (like SPI, TWI, and TRACE) require the use of specific dedicated clock pins. These pins are optimized for timing and are marked with a cross in the pin assignment tables. All peripherals with clock signals must use these dedicated pins.
3. General-purpose GPIO usage – All port pins can be used as GPIO pins. However, P2 pins do not support Sense/DETECT or GPIOTE functionality.
4. Dedicated pin assignments – Certain peripherals have dedicated pins that they must use. This is documented in the Hardware and layout -> Pin assignments chapter for every SoC datasheet.
   • FLPR – Uses dedicated pins on P2 (except for nRF54LV10A, which uses P1).
   • SPIM00/UARTE00 – Uses dedicated pins on P2.
   • GRTC – Has dedicated pins for clock and PWM output (if used) on P0, and a dedicated pin for CLK16M on P1 (if used).
   • TAMPC, NFC, RADIO – These peripherals use dedicated pins on P1, with RADIO pins specifically required for direction finding.
5. Fixed-function pins – Certain pins on all packages are designated as non-GPIO and have fixed functions that cannot be altered. These include power and ground pins, crystal oscillator pins, decoupling and regulator pins, the RF antenna pin (ANT pin), the reset pin, USB pins (nRF54LM20A|B), and the Serial Wire Debug pin.

A note on GPIOTE support

A GPIO port provides the direct, low-level control and configuration of individual physical pins (grouped into up to 32 pins) on the device using registers that are written or read by the CPU. On the other hand, GPIOTE is a supporting component for a GPIO port. It allows for GPIO operations to be integrated into the Distributed Programmable Peripheral Interconnect (DPPI) system, enabling the access to pins using tasks and events without direct CPU intervention for every event.