nRF54L Series Express

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Power domains

The nRF54L Series architecture is divided into four power domains.

A power domain is a large section of a chip that can be independently powered on or off to optimize energy consumption.

The hardware manages power domains automatically. When no component within a power domain is active, the entire domain is shut down. All registers in the domain retain their value while shut down. If a component in that domain is activated (for example, by writing to a peripheral register, or through the event system), the power domain automatically powers up. This functionality not only reduces overall power consumption but also significantly lowers leakage current in sleep mode.

Let’s take a look at the four power domains in the nRF54L Series architecture:

MCU domain (MCU)

  • This domain houses the Arm Cortex-M33 processor, the RISC-V coprocessor, and a debug system. It also contains high-speed peripherals (for example, UARTE and HS-SPI), the Cryptographic Accelerator Engine (CRACEN), high-speed USB (exclusive to the nRF54LM20A | nRF54LM20B SoCs), Axon neural processing unit – NPU (exclusive to the nRF54LM20B SoC).
  • The MCU domain operates on a 128 MHz clock.
  • Peripherals in this domain that have a numeric ID start with the number 0 (for example, UARTE00).
  • This domain has a dedicated GPIO port, which is port 2 (P2). P2 does not exist on the nRF54LV10A.

Radio domain (RADIO)

  • This domain contains the 2.4 GHz radio and peripherals that support the radio protocol stack.
  • The radio domain runs at 32 MHz.
  • Peripherals in this domain that have a numeric ID start with the number 1 (for example, TIMER10).
  • Since all the peripherals inside it are meant to support the radio, this domain does not have a dedicated GPIO port.

Peripheral domain (PERI)

  • This domain contains most of the peripherals on the chip.
  • The peripheral domain operates at 16 MHz.
  • Peripherals in this domain that have a numeric ID start with the number 2 (for example, UARTE20).
  • This domain has dedicated GPIO ports: port 1 (P1) and port 3 (P3), with P3 available only on the nRF54LM20A|B SoCs.

Low-power domain (LP)

  • This domain is dedicated to peripherals designed for ultra-low power modes. It can wake up the rest of the system even if the peripheral domain is powered off.
  • It runs at 16 MHz.
  • Peripherals in this domain that have a numeric ID start with the number 3 (for example, UARTE30).
  • This domain has a dedicated GPIO port, which is port 0 (P0).

The following block diagrams detail the available power domains along with their components and peripherals for the nRF54L Series. The diagram varies depending on the device:

nRF54LM20B
nRF54LM20B block diagram
nRF54LM20A
nRF54LM20A block diagram
Tab Header
nRF54L15 | nRF54L10 | nRF54L05 block diagram
Tab Header
nRF54LV10A block diagram
Tab Header
nRF54LS05A | nRF54LS05B block digram

As a system designer or architect aiming to optimize power consumption in your designs, it is crucial to strategically select and group peripherals within the same power domain. This allows the system to keep fewer domains powered on, optimizing overall current consumption.

Example scenario: Your application needs to use a standard UART and a TIMER simultaneously.

  • From a low-power perspective, it makes sense to choose UARTE20 and TIMER20, (or any other timer in the PERI domain) since both are in the same domain, which is the PERI domain.
  • You could also pair UARTE20 with TIMER00 from the MCU domain. However, this would necessitate keeping multiple domains active, thus increasing power consumption.

Using an SoC with multiple power domains offers a significant benefit, primarily enabling low-power operation. By allowing domains to be powered independently, large sections of the chip can be turned off when not actively needed, helping achieve lower power consumption. This leads to improved battery lifetime and potentially reduced battery size. The low-power domain, in particular, contains peripherals specifically designed for ultra-low power modes and can wake the rest of the system even when the peripheral domain is powered off.

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